The invention relates to systems employing active and standby processors, and more particularly relates to the writing of data from the active processor to the standby processor so that the latter processor may track accurately the activity of the former processor.
Many different systems, e.g., computer processing systems, communication systems, etc., employ redundant system processors for reliability purposes. Typically, the processors are respectively designated the active and standby processors, in which the active processor controls the operation of the system and the standby processor monitors the health of the active processor. The standby processor assumes an active state whenever diagnostic processes indicate that the active processor is faulty. To help ensure that its transition from the standby state to the active state does not impact the system, the standby processor continually tracks the activity of the active processor. The standby processor does this by monitoring the writing of certain data pertaining to the system in memory, as is shown in FIG. 1.
In particular, operational system 300 includes, inter alia, the underlying system 250 whose operation is controlled by redundant controllers (processors) 100 and 200. Each of the controllers include, inter alia, a processor (105, 205), memory (110, 210) and shadow processor (120, 220). Assume that controllers 100 are respectively designated as active and standby. In the active state, shadow processor 120 monitors the data that system processor 105 writes into memory 110 via bus 115. If shadow processor 120 finds that data is being written into one of a predetermined group of memory 110 locations, then shadow processor 120 passes the write address and data to shadow processor 220 via path 121. The write address and data is loaded into a conventional FIFO within processor 220. Processor 220 unloads such data from its FIFO and stores it via bus 215 in a memory 210 location specified by the address accompanying the data. To do so, processor 220 must contend with system processor 205 for access to bus 215. If processor 205 is also contending for bus 215, and the active system processor 105 is storing an appreciable amount of data in the aforementioned group of memory 110 locations, then it is possible that shadow processor 220 might not be able to access bus 215 frequently enough to keep pace with the loading of shadow data in its FIFO. Consequently, data may be lost when the FIFO overflows, which would seriously impact the ability of standby controller 200 to track active controller 100.
I address the above problem and advance the relevant art by controlling the speed at which the active processor is writing data into the monitored memory locations whenever the number of memory locations containing unloaded data in the FIFO of the standby shadow processor reaches a predetermined level. In accordance with an aspect of the invention, the active processor monitors the number of locations of the standby FIFO that are filled and invokes such control when it detects that that number has reached the aforementioned predetermined level. In accordance with another aspect of the invention, the active shadow processor exercises such control by contending for access to the memory access bus and xe2x80x9choldingxe2x80x9d onto the bus for a brief period of time sufficient to allow the standby shadow processor enough time to unload its FIFO below a certain point.
These and other aspects of the claimed invention will be appreciated from the following detailed description read in conjunction with the accompanying drawings.